Senior Logic Design Engineer, Cache Coherent Interconnects

Responsibilities

• As a member of our core CPU team, you'll own and be responsible for crafting and timely delivery of a specific unit on the chip.
• Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing closure, and design documentation.
• Collaborate with our verification team to verify the correctness of your unit.
• Work with implementation to achieve your timing, area, performance and power goals.
• Assist with timing closure of super units.
• What we need to see
• Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
• 5+ years of experience in processor or other related high performance semiconductor designs.
• Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
• Strong communication and interpersonal skills are required along with the work in a dynamic, global team. Your successful track record of mentoring junior engineers and interns a huge plus.

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